This course covers the whole syllabus of Network Theory&nbsp;for GATE&nbsp;which consists of Approximately 10 marks for&nbsp;EC, EE, IN and BM branch.&nbsp;
In this course you will get :&nbsp;
Complete Video Lectures&nbsp;: 70 Hrs of Video Lectures Covering the complete syllabus of Network Theory&nbsp;for GATE/ESE/PSU Examination.&nbsp;
Lecture Notes&nbsp;:&nbsp;Neatly Written and Downloadable Lecture Notes of each topic. It&#39;s recommended to get the Hardcopy of the Lecture Notes before the start of the lecture.&nbsp;
Doubt Solving Classes&nbsp;:&nbsp;Doubt Support provided on WhatsApp Group by Himanshu Agarwal and Anish Saha. Live Doubt Solving Classes to be Conducted when Required.
Test Series&nbsp;: 10+ Topic wise and Subject wise test series will be provided comprising excellent exam oriented questions specially designed by Himanshu Agarwal and Anish Saha.
Topics Covered :
Basics of Network - 13 Hrs
Network Theorem - 7 Hrs
Transient Analysis - 30 Hrs
Phasor Diagram &amp; Locus Diagram - 8&nbsp;Hrs
Complex Power - 4.5 Hrs
Resonance - 6&nbsp;Hrs
Network Theorems in AC - 2.5&nbsp;Hr
TWO-Port Networks - 8&nbsp;Hrs
3-Phase Circuits - 2 Hrs
Mode of Communication : English
Validity : 31st March, 2026

Network Theory For GATE 2026

PrepFusion

🚀 Welcome to the Digital Design with Verilog a Free VLSI Placement Series! This comprehensive course is designed to help you ace your GATE, VLSI, and placement exams. Learn Verilog from the ground up, covering gate-level, dataflow, and behavioral modeling, along with combinational &amp; sequential circuits, memories, and FSMs. This series includes live coding demos, detailed notes (black &amp; white background for easy viewing), and a day-wise study plan to maximize your learning.
📌 What you&#39;ll learn:
<ul>
	<li>Verilog Basics&nbsp;</li>
	<li>Gate-level, Dataflow,</li>
	<li>Behavioral Modeling</li>
	<li>Combinational &amp; Sequential Circuits</li>
	<li>Memories and FSMs (Finite State Machines)</li>
</ul>
 
📌 Course Features :
<ul>
	<li>Recorded Lectures</li>
	<li>Live Coding Demos&nbsp;</li>
	<li>Notes</li>
	<li>Day-wise Study Plan</li>
</ul>
&nbsp;
&nbsp;

Digital Design With Verilog : Module - 1

Mathematics Foundation For GATE

This course covers the whole syllabus of Electrical Machines for GATE&nbsp;which consists of Approximately 10 marks for&nbsp;&nbsp;EE&nbsp;and IN branch.&nbsp;
In this course you will get :&nbsp;
Complete Video Lectures&nbsp;: 10&nbsp;Hrs of Video Lectures Covering the complete syllabus of Electrical Machines&nbsp;for GATE/ESE/PSU Examination.&nbsp;
Lecture Notes&nbsp;:&nbsp;Neatly Written and Downloadable Lecture Notes of each topic. It&#39;s recommended to get the Hardcopy of the Lecture Notes before the start of the lecture.&nbsp;
Mode of Communication&nbsp;: English&nbsp;

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<table border="1" cellpadding="0" cellspacing="0">
	<tbody>
		<tr>
			<td style="text-align:center">Total Duration</td>
			<td style="text-align:center">105:30:27</td>
		</tr>
		<tr>
			<td style="text-align:center">Magnetic circuits</td>
			<td style="text-align:center">8:46:42</td>
		</tr>
		<tr>
			<td style="text-align:center">Transformers</td>
			<td style="text-align:center">27:27:02</td>
		</tr>
		<tr>
			<td style="text-align:center">DC machines</td>
			<td style="text-align:center">24:07:45</td>
		</tr>
		<tr>
			<td style="text-align:center">Introduction machines</td>
			<td style="text-align:center">17:12:45</td>
		</tr>
		<tr>
			<td style="text-align:center">Synchronous machines&nbsp; &nbsp;</td>
			<td style="text-align:center">&nbsp;24:38:33</td>
		</tr>
		<tr>
			<td style="text-align:center">Miscellaneous topics</td>
			<td style="text-align:center">3:17:40</td>
		</tr>
	</tbody>
</table>
&nbsp;

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