Digital Design With Verilog & COA

Description

Validity : 3 Months / 6 Months (Based on your Selection)

This course covers the whole syllabus of Verilog HDL & COA(Computer Organization & Architechture) For Campus Placements

With this course, students will be able to prepare themselves for Digital Design Interviews, M.tech/MS Admission interviews,

The course curriculum is Strictly adhered for Freshers. This course is NOT for Industry experts.

Lecture Notes : Neatly Written and Downloadable Lecture Notes of each topic. It's recommended to get the Hardcopy of the Lecture Notes before the start of the lecture. 

Doubt Solving Classes :Doubt Support provided on WhatsApp Group by Himanshu Agarwal and Anish Saha.

Mode of Communication : English

Verilog HDL & COA :  Test Series Included

Module 1 (14 Hours) :

VLSI Design Flow
Levels of Abstraction
Values and Signals In Verilog
Keywords & Tokens in Verilog
Event Control
Data Types
Vectors, Arrays, Memories, Parameters
GATE Level Modeling
Continuous Assignments, Operators & Operands

Module 2 (15 Hours) :

Behavioral Modeling
Procedural Assignments
Loops, Parallel & Generate Blocks
Combinational Block Designs:
MUX, Counter, Decoder and Encoder Design
Comparator, 8-Bit Barrel Shifter
Sequential Block Designs: D-Flip Flop, Frequency Divider
Memory Elements Design :  FIFO, RAM(Single & Dual Port)
Finite State Machines(FSM) : Mealy & Moore, Vending Machine & Traffic Control Design
Module-2 Exercise Solutions

COA(Computer Organization & Architecture) : 45 HOURS 

Chapter - 1 : 
CPU Architechtures, Instruction Based On Operands, Instruction Cycle, Addressing Modes
Chapter - 2 : Datapath, Control Unit(CU), Instruction Pipelining
Chapter - 3 : Non - Synchronized Pipelines
Chapter - 4 : Floating Point Representation {Important For GATE ECE}
Chapter - 5 : IO Memory Organization
Chapter - 6 : Cache Memory {Very Important For Placements}

Computer Architecture 9:30:27
Control unit,Instruction Pipeline 9:55:23
Non-Synchronized Pipeline 3:06:45
Floating Point Representation 4:34:23
IO memory Organization 8:30:00
Cache Memory 10:47:50
Total Hours 46:24:48

Content

1. Verilog HDL

25 videos4 files

2. COA(Computer Organization & Architecture)

29 videos12 files

Digital Design With Verilog & COA

$32.66$62.0948% off
Have a coupon?

$32.66