Validity : 3 Months / 6 Months (Based on your Selection)

This course covers the whole syllabus of Verilog HDL For Campus Placements

With this course, students will be able to prepare themselves for Digital Design Interviews, M.tech/MS Admission interviews,

The course curriculum is Strictly adhered for Freshers. This course is NOT for Industry experts.

Lecture Notes : Neatly Written and Downloadable Lecture Notes of each topic. It's recommended to get the Hardcopy of the Lecture Notes before the start of the lecture. 

Doubt Solving Classes :Doubt Support provided on WhatsApp Group by Himanshu Agarwal and Anish Saha.

Mode of Communication : English

Verilog HDL :  (Test Series To Be Uploaded by April End)

Module 1 (14 Hours) :

VLSI Design Flow
Levels of Abstraction
Values and Signals In Verilog
Keywords & Tokens in Verilog
Event Control
Data Types
Vectors, Arrays, Memories, Parameters
GATE Level Modeling
Continuous Assignments, Operators & Operands

Module 2 (15 Hours) :

Behavioral Modeling
Procedural Assignments
Loops, Parallel & Generate Blocks
Combinational Block Designs:
MUX, Counter, Decoder and Encoder Design
Comparator, 8-Bit Barrel Shifter
Sequential Block Designs: D-Flip Flop, Frequency Divider
Memory Elements Design :  FIFO, RAM(Single & Dual Port)
Finite State Machines(FSM) : Mealy & Moore, Vending Machine & Traffic Control Design
Module-2 Exercise Solutions